In the field of 8-bit and 16-bit microcontroller control units (MCUs), there is an increasing trend towards integrating ever-larger memory elements onto the MCUs, and accessing the data elements/individual addresses in these larger memory elements. For example, there is a consumer-driven demand to provide 128 Kbyte memory, and potentially 256 Kbytes (and more), of memory on an 8/16-bit MCU.
 8/16-bit MCUs typically have a program counter that comprises 16-bits and instructions with addressing modes that only cater for up to a 16-bit address. This results in an addressable limit of 65,536 locations (i.e. the number of combinations of 16 0's and 1's). Thus, it is known that the program counter associated with MCUs is the limiting factor in accessing physical address space and consequently many current 8/16-bit MCUs are limited in that they are unable to support addressing an associated memory above 64 Kbytes.
Within MCUS, it is also known that a number of memory management units (MMUs) exist that comprise paging access mechanisms to access paged memory. However, it is also known that these paging access mechanisms fail to support accessing a particular memory line for data access in an efficient and easily usable manner.
Paged memory (sometimes referred to as banked memory) is a term that is used to describe a remapping of physical memory to an address within the address capability of the MCU device. An example of code required to access data in such a paged memory would typically be of the form illustrated in FIG. 1.
A page is typically a specific size, which is less than the addressable memory range of the device but is less than the physical address space desired. When accessing physical memory through this ‘page’ it may be necessary to re-map another page into the page's area, if the next sequential byte required is not within the current page. In addition, the index pointing to the paged memory typically needs to be adjusted to point to the start of the paged memory. Access to memory is non-linear and non-contiguous.
In typical paged memory designs there are two major issues in accessing paged memory for data, where both issues are known to severely impact performance:                (i) If code is executing from paged memory it is necessary to call a routine in unpaged memory to access data in another page, and make this available to the calling code.        (ii) As is often the case, data cannot fit within a single page and, thus, spans multiple pages. As a consequence, access mechanisms are very limited to accessing a particular page, for example accessing only 4K of memory, or a significant amount of effort is expended in order to access (for example check and update the page and pointer) data within the page space that crosses multiple pages.        
Thus, a need exists for a microprocessor memory management unit and mechanism therefor that enables data in memory space to be accessed in a more efficient manner.